74hc4075-q100; 74hct4075-q100 triple 3-input or gate
74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate Rev. 1 — 22 May 2013 Product data sheet 1. General description
The 74HC4075-Q100; 74HCT4075-Q100 is a triple 3-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Complies with JEDEC standard JESD7A Input levels:
For 74HC4075-Q100: CMOS level For 74HCT4075-Q100: TTL level
MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
3. Ordering information Ordering information Type number Temperature range Description
plastic small outline package; 14 leads;
plastic thin shrink small outline package;
NXP Semiconductors 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate 4. Functional Logic symbol IEC logic symbol Logic diagram (one gate) 5. Pinning information 5.1 Pinning +&4 +&74 +&4 +&74 Pin configuration SO14 Pin configuration TSSOP14 5.2 Pin description Pin description Description
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NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 22 May 2013 NXP Semiconductors 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate 6. Functional description Function sele
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).Parameter Conditions
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
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NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 22 May 2013 NXP Semiconductors 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate 8. Recommended operating conditions Recommended operating conditions Voltages are referenced to GND (ground = 0 V)Symbol Parameter Conditions 74HC4075-Q100 74HCT4075-Q100 9. Static characteristics Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V).Symbol Parameter Conditions
40 C to +85 C 40 C to +125 C Unit 74HC4075-Q100
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NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 22 May 2013 NXP Semiconductors 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V).Symbol Parameter Conditions
40 C to +85 C 40 C to +125 C Unit 74HCT4075-Q100
other inputs at VCC or GND; VCC = 4.5 V to 5.5 V
10. Dynamic characteristics Dynamic characteristics GND = 0 V; CL = 50 pF; for test circSymbol Parameter Conditions
40 C to +125 C Unit (85 C) (125 C) 74HC4075-Q100
power dissipation per package; VI = GND to VCC
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NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 22 May 2013 NXP Semiconductors 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate Dynamic characteristics …continued GND = 0 V; CL = 50 pF; for test circuit see Figure 7.Symbol Parameter Conditions
40 C to +125 C Unit (85 C) (125 C) 74HCT4075-Q100
CPD is used to determine the dynamic power dissipation (PD in W):P
fi = input frequency in MHz;fo = output frequency in MHz;CL = output load capacitance in pF;VCC = supply voltage in V;N = number of inputs switching; (C
11. Waveforms
VOL and VOH are typical voltage output levels that occur with the output load. Input to output propagation delays Measurement points
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NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 22 May 2013 NXP Semiconductors 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance. Test circuit for measuring switching times Test data
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NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 22 May 2013 NXP Semiconductors 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 DIMENSIONS (inch dimensions are derived from the original mm dimensions)
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES EUROPEAN ISSUE DATE PROJECTION Package outline SOT108-1 (SO14)
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NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 22 May 2013 NXP Semiconductors 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 DIMENSIONS (mm are the original dimensions)
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. REFERENCES EUROPEAN ISSUE DATE PROJECTION Package outline SOT402-1 (TSSOP14)
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NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 22 May 2013 NXP Semiconductors 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate 13. Abbreviations Table 10. Abbreviations Description
Low-power Schottky Transistor-Transistor Logic
14. Revision history
Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes
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NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 22 May 2013 NXP Semiconductors 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate 15. Legal information 15.1 Data Document status Product statu Definition
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NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 22 May 2013 NXP Semiconductors 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate No offer to sell or license — Nothing in this document may be interpreted or Translations — A non-English (translated) version of a document is for
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NXP B.V. 2013. All rights reserved. Product data sheet Rev. 1 — 22 May 2013 NXP Semiconductors 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate 17. Contents
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Date of release: 22 May 2013 Document identifier: 74HC_HCT4075_Q100
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